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1 for more information www.linear.com/LTC2337-18 typical a pplica t ion fea t ures descrip t ion 18-bit, 500ksps, 10.24v true bipolar, fully differential input adc with 100db snr the lt c ? 2337-18 is a low noise, high speed 18- bit succes- sive approximation register ( sar) adc with fully differential inputs. operating from a single 5 v supply, the LTC2337-18 has a 10.24 v true bipolar input range, making it ideal for high voltage applications which require a wide dynamic range. the LTC2337-18 achieves 4 lsb inl maximum, no missing codes at 18-bits with 100db snr. the LTC2337-18 has an onboard single-shot capable reference buffer and low drift (20 ppm/c max) 2.048v temperature compensated reference. the LTC2337-18 also has a high speed spi-compatible serial interface that supports 1.8v, 2.5v, 3.3 v and 5 v logic while also featuring a daisy-chain mode. the fast 500 ksps throughput with no cycle latency makes the LTC2337-18 ideally suited for a wide variety of high speed applications. an internal oscillator sets the conversion time, easing external timing considerations. the LTC2337-18 dissipates only 35mw and automatically naps between conversions, leading to reduced power dissipation that scales with the sampling rate. a sleep mode is also provided to reduce the power consumption of the LTC2337-18 to 300 w for further power savings during inactive periods. l, lt , lt c , lt m , linear technology and the linear logo are registered trademarks and softspan is a trademark of linear t echnology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents, including 7705765 and 7961132 a pplica t ions n 500ksps throughput rate n 4lsb inl (max) n guaranteed 18-bit no missing codes n fully differential inputs n true bipolar input ranges 6.25 v , 10.24v , 12.5v n 100db snr ( typ ) at f in = 2khz n C115db thd ( typ ) at f in = 2khz n guaranteed operation to 125c n single 5v supply n low drift (20ppm/c max) 2.048v internal reference n onboard single-shot capable reference buffer n no pipeline delay, no cycle latency n 1.8 v to 5v i/o voltages n spi-compatible serial i/o with daisy-chain mode n internal conversion clock n power dissipation 35mw ( typ ) n 16-lead msop package n programmable logic controllers n industrial process control n high speed data acquisition n portable or compact instrumentation n ate 32k point fft f s = 500ksps, f in = 2khz +10.24v ?10.24v +10.24v ?10.24v ? + sample clock 233718 ta01 10f 0.1f 5v ref 1.8v to 5v 47f refbuf gnd chain rdl/sdi sdo sck busy cnv LTC2337-18 v dd 2.2f 100nf refin v ddlbyp ov dd in + in ? ?180 amplitude (dbfs) ?60 ?40 ?20 ?80 ?100 ?120 ?140 ?160 0 233718 ta01b snr = 100.4db thd = ?116db sinad = 100.3db sfdr = ?118db frequency (khz) 0 50 100 150 250 200 ltc 2337-18 233718f
2 for more information www.linear.com/LTC2337-18 p in c on f igura t ion a bsolu t e maxi m u m r a t ings supply voltage (v dd ) .................................................. 6v su pply voltage ( ov dd ) ................................................ 6v su pply bypass voltage (v ddlbyp ) ........................... 3.2 v a nalog input voltage in + , in C .............................................. C16 .5 v to 16.5 v refbuf ................................................................... 6 v refin .................................................................. 2. 8 v digital input voltage ( note 3) ........................... ( gn d C0.3 v) to ( ov dd + 0.3 v) digital output voltage ( note 3) ........................... ( gn d C0.3 v) to ( ov dd + 0.3 v) power dissipation .............................................. 50 0 mw operating temperature range ltc 2 337 c ................................................ 0 c to 70 c ltc 2 337 i ............................................. C4 0 c to 85 c ltc 2 337 h .......................................... C 40 c to 125 c storage temperature range .................. C 65 c to 150 c (notes 1, 2) 1 2 3 4 5 6 7 8 v ddlbyp v dd gnd in + in ? gnd refbuf refin 16 15 14 13 12 11 10 9 gnd ov dd sdo sck rdl/sdi busy chain cnv top view ms package 16-lead plastic msop t jmax = 150c, ja = 110c/w o r d er i n f or m a t ion lead free finish tape and reel part marking* package description temperature range ltc2337cms-18#pbf ltc2337cms-18#trpbf 233718 16-lead plastic msop 0c to 70c ltc2337ims-18#pbf ltc2337ims-18#trpbf 233718 16-lead plastic msop C40c to 85c ltc2337hms-18#pbf ltc2337hms-18#trpbf 233718 16-lead plastic msop C40c to 125c consult lt c marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container . consult lt c marketing for information on nonstandard lead based finish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ ltc 2337-18 233718f
3 for more information www.linear.com/LTC2337-18 e lec t rical c harac t eris t ics c onver t er c harac t eris t ics dyna m ic a ccuracy the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 4) the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 4) the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c and a in = C1dbfs. (notes 4, 8) symbol parameter conditions min typ max units v in + absolute input range (in + ) (note 5) l C2.5 ? v refbuf C 0.25 2.5 ? v refbuf + 0.25 v v in C absolute input range (in C ) (note 5) l C2.5 ? v refbuf C 0.25 2.5 ? v refbuf + 0.25 v v in + C v in C input differential voltage range v in = v in + C v in C l C5 ? v refbuf 5 ? v refbuf v v cm common mode input range (note 11) l C0.5 0 0.5 v i in analog input current l C7.8 4.8 ma c in analog input capacitance 5 pf r in analog input resistance 2.083 k cmrr input common mode rejection ratio f in = 250khz 67 db symbol parameter conditions min typ max units resolution l 18 bits no missing codes l 18 bits transition noise 0.8 lsb rms inl integral linearity error (note 6) l C4 1 4 lsb dnl differential linearity error l C1 0.1 1 lsb bze bipolar zero-scale error (note 7) l C15 0 15 lsb bipolar zero-scale error drift 0.01 lsb/c fse bipolar full-scale error v refbuf = 4.096v (refbuf overdriven) (notes 7, 9) l C100 100 lsb refin = 2.048v (note 7) l C150 150 lsb bipolar full-scale error drift 0.5 ppm/c symbol parameter conditions min typ max units sinad signal-to-(noise + distortion) ratio 6.25v range, f in = 2khz, refin = 1.25v l 93 97 db 10.24v range, f in = 2khz, refin = 2.048v l 95 100 db 12.5v range, f in = 2khz, refbuf = 5v l 96 101 db snr signal-to-noise ratio 6.25v range, f in = 2khz, refin = 1.25v l 93.5 97 db 10.24v range, f in = 2khz, refin = 2.048v l 96 100 db 12.5v range, f in = 2khz, refbuf = 5v l 98 102 db thd total harmonic distortion 6.25v range, f in = 2khz, refin = 1.25v l C111 C102 db 10.24v range, f in = 2khz, refin = 2.048v l C115 C102 db 12.5v range, f in = 2khz, refbuf = 5v l C112 C100 db sfdr spurious free dynamic range 6.25v range, f in = 2khz, refin = 1.25v l 102 113 db 10.24v range, f in = 2khz, refin = 2.048v l 102 117 db 12.5v range, f in = 2khz, refbuf = 5v l 100 114 db C3db input linear bandwidth 7 mhz aperture delay 500 ps aperture jitter 4 ps transient response full-scale step 0.5 s ltc 2337-18 233718f
4 for more information www.linear.com/LTC2337-18 i n t ernal r e f erence c harac t eris t ics r e f erence b u ff er c harac t eris t ics digi t al i npu t s an d digi t al o u t pu t s p ower r equire m en t s the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 4) the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 4) the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 4) the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 4) symbol parameter conditions min typ max units v refin internal reference output voltage 2.043 2.048 2.053 v v refin temperature coefficient (note 14) l 2 20 ppm/c refin output impedance 15 k v refin line regulation v dd = 4.75v to 5.25v 0.08 mv/v refin input voltage range (refin overdriven) (note 5) 1.25 2.4 v symbol parameter conditions min typ max units v refbuf reference buffer output voltage v refin = 2.048v l 4.091 4.096 4.101 v refbuf input voltage range (refbuf overdriven) (notes 5, 9) l 2.5 5 v refbuf output impedance v refin = 0v 13 k i refbuf refbuf load current v refbuf = 5v (refbuf overdriven) (notes 9, 10) v refbuf = 5v, nap mode (refbuf overdriven) (note 9) l 0.72 0.39 0.8 ma ma symbol parameter conditions min typ max units v ih high level input voltage l 0.8 ? ov dd v v il low level input voltage l 0.2 ? ov dd v i in digital input current v in = 0v to ov dd l C10 10 a c in digital input capacitance 5 pf v oh high level output voltage i o = C500a l ov dd C 0.2 v v ol low level output voltage i o = 500a l 0.2 v i oz hi-z output leakage current v out = 0v to ov dd l C10 10 a i source output source current v out = 0v C10 ma i sink output sink current v out = ov dd 10 ma symbol parameter conditions min typ max units v dd supply voltage l 4.75 5 5.25 v o vdd supply voltage l 1.71 5.25 v i vdd i ovdd i nap i sleep supply current supply current nap mode current sleep mode current 500 ksps sample rate (in + = in C = 0v) 500ksps sample rate (c l = 20pf) conversion done (i vdd + i ovdd ) sleep mode (i vdd + i ovdd ) l l l 7 0.1 3.9 60 8.5 4.6 225 ma ma ma a p d power dissipation nap mode sleep mode 500 ksps sample rate (in + = in C = 0v) conversion done (i vdd + i ovdd ) sleep mode (i vdd + i ovdd ) l l l 35 19.5 0.3 42.5 23 1.1 mw mw mw ltc 2337-18 233718f
5 for more information www.linear.com/LTC2337-18 a d c ti m ing c harac t eris t ics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 4) note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: all voltage values are with respect to ground. note 3: when these pin voltages are taken below ground or above v dd or ov dd , they will be clamped by internal diodes. this product can handle input currents up to 100ma below ground or above v dd or ov dd without latch-up. note 4: v dd = 5v, ov dd = 2.5v, 10.24v range, refin = 2.048v, f smpl = 500khz. note 5: recommended operating conditions. note 6: integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. the deviation is measured from the center of the quantization band. note 7: bipolar zero error is the offset voltage measured from C0.5lsb when the output code flickers between 00 0000 0000 0000 0000 and 11 1111 1111 1111 1111. full-scale bipolar error is the worst-case of Cfs or +fs untrimmed deviation from ideal first and last code transitions and includes the effect of offset error. note 8: all specifications in db are referred to a full-scale 20.48v input with refin = 2.048v. note 9: when refbuf is overdriven, the internal reference buffer must be turned off by setting refin = 0v. note 10: f smpl = 500khz, i refbuf varies proportionally with sample rate. note 11: guaranteed by design, not subject to test. note 12: parameter tested and guaranteed at ov dd = 1.71v, ov dd = 2.5v and ov dd = 5.25v. note 13: t sck of 10ns maximum allows a shift clock frequency up to 100mhz for rising edge capture. note 14: temperature coefficient is calculated by dividing the maximum change in output voltage by the specified temperature range. symbol parameter conditions min typ max units f smpl maximum sampling frequency l 500 ksps t conv conversion time l 1 1.5 s t acq acquisition time t acq = t cyc C t hold (note 11) l 1.460 s t hold maximum time between acquisitions l 540 ns t cyc time between conversions l 2 s t cnvh cnv high time l 20 ns t busylh cnv to busy delay c l = 20pf l 13 ns t cnvl minimum low time for cnv (note 12) l 20 ns t quiet sck quiet time from cnv (note 11) l 20 ns t sck sck period (notes 12, 13) l 10 ns t sckh sck high time l 4 ns t sckl sck low time l 4 ns t ssdisck sdi setup time from sck (note 12) l 4 ns t hsdisck sdi hold time from sck (note 12) l 1 ns t sckch sck period in chain mode t sckch = t ssdisck + t dsdo l 13.5 ns t dsdo sdo data valid delay from sck c l = 20pf, ov dd = 5.25v c l = 20pf, ov dd = 2.5v c l = 20pf, ov dd = 1.71v l l l 7.5 8 9.5 ns ns ns t hsdo sdo data remains valid delay from sck c l = 20pf (note 11) l 1 ns t dsdobusyl sdo data valid delay from busy c l = 20pf (note 11) l 5 ns t en bus enable time after rdl (note 12) l 16 ns t dis bus relinquish time after rdl (note 12) l 13 ns t wake refbuf wakeup time c refbuf = 47f, c refin = 100nf 200 ms figure 1. voltage levels for timing specifications 0.8 ? ov dd 0.2 ? ov dd 50% 50% 233718 f01 0.2 ? ov dd 0.8 ? ov dd 0.2 ? ov dd 0.8 ? ov dd t delay t width t delay ltc 2337-18 233718f
6 for more information www.linear.com/LTC2337-18 typical p er f or m ance c harac t eris t ics 32k point fft f s = 500ksps, f in = 2khz snr, sinad vs input frequency thd, harmonics vs input frequency snr, sinad vs input level, f in = 2khz snr, sinad vs temperature, f in = 2khz thd, harmonics vs temperature, f in = 2khz integral nonlinearity vs output code differential nonlinearity vs output code dc histogram t a = 25c, v dd = 5v, ov dd = 2.5v, refin = 2.048v, f smpl = 500ksps, unless otherwise noted. ?180 amplitude (dbfs) ?60 ?40 ?20 ?80 ?100 ?120 ?140 ?160 0 233718 g04 snr = 100.4db thd = ?116db sinad = 100.3db sfdr = ?118db frequency (khz) 0 50 100 150 250 200 input level (db) magnitude (dbfs) 102.0 233718 g07 100.0 100.5 101.0 101.5 ?40 ?30 ?20 ?10 0 snr sinad temperature (c) ?55 ?35 ?15 5 25 45 65 85 105 125 snr, sinad (dbfs) 102.0 101.5 101.0 100.5 233718 g08 98.0 98.5 99.0 99.5 100.0 sinad snr temperature (c) ?55 ?35 ?15 5 25 45 65 85 105 125 thd, harmonics (dbfs) ?105 ?110 233718 g09 ?135 ?130 ?125 ?120 ?115 3rd 2nd thd frequency (khz) snr, sinad (dbfs) 110 233718 g05 60 70 80 100 90 0 25 50 75 150125100 175 200 snr sinad frequency (khz) thd, harmonics (dbfs) ?70 ?80 233718 g06 ?150 ?140 ?120 ?130 ?110 ?100 ?90 0 25 50 10075 150125 175 200 3rd 2nd thd code 131075 131073 131071 131069 131067 0 counts 2000 1000 500 4500 3000 2500 1500 3500 4000 5000 233718 g03 = 0.8 output code ?3.0 inl error (lsb) 2.5 2.0 1.5 1.0 0 ?2.5 ?2.0 ?1.5 ?0.5 0.5 ?1.0 3.0 233718 g01 0 65536 131072 196608 262144 output code ?0.5 dnl error (lsb) 0.4 0.3 0.2 0.1 0.0 ?0.4 ?0.3 ?0.2 ?0.1 0.5 233718 g02 0 65536 131072 196608 262144 ltc 2337-18 233718f
7 for more information www.linear.com/LTC2337-18 typical p er f or m ance c harac t eris t ics supply current vs temperature sleep current vs temperature internal reference output vs temperature internal reference output temperature coefficient distribution cmrr vs input frequency supply current vs sampling rate inl/dnl vs temperature full-scale error vs temperature offset error vs temperature t a = 25c, v dd = 5v, ov dd = 2.5v, refin = 2.048v, f smpl = 500ksps, unless otherwise noted. temperature (c) ?55 ?35 ?15 5 25 45 65 85 105 125 inl, dnl error (lsb) 2.0 1.5 1.0 0.5 233718 g10 ?2.0 ?1.5 ?1.0 ?0.5 0 max inl max dnl min inl min dnl temperature (c) current (ma) 8 7 6 233718 g13 0 1 2 3 4 5 ?55 ?35 ?15 5 25 45 65 85 105 125 v dd ov dd temperature (c) current (a) 120 233718 g14 0 20 40 60 80 100 ?55 ?35 ?15 5 25 45 65 85 105 125 frequency (khz) 0 100 50 150 200 250 50 cmrr (db) 65 60 55 80 75 70 233718 g17 233718 g15 temperature (c) ?55 ?35 ?15 5 25 45 65 85 105 125 internal reference output (v) 2.0484 2.0483 2.0482 2.0481 2.0476 2.0477 2.0478 2.0479 2.0480 sampling frequency (khz) 0 supply current (ma) 8 7 6 5 3 1 4 2 0 400 200 233718 g18 500 300 100 v dd ov dd 233718 g11 temperature (c) ?55 ?35 ?15 5 25 45 65 85 105 125 full-scale error (lsb) 20 15 10 5 ?20 ?15 ?10 ?5 0 233718 g12 temperature (c) ?55 ?35 ?15 5 25 45 65 85 105 125 offset error (lsb) 5 4 3 2 1 ?5 ?4 ?3 ?2 ?1 0 drift (ppm/c) number of parts 35 30 233718 g16 0 5 10 15 20 25 ?10 ?8 ?6 ?2?4 20 4 6 8 10 ltc 2337-18 233718f
8 for more information www.linear.com/LTC2337-18 p in func t ions v ddlbyp (pin 1): 2.5 v supply bypass pin. the voltage on this pin is generated via an onboard regulator off of v dd . this pin must be bypassed with a 2.2 f ceramic capacitor to gnd. v dd (pin 2): 5 v power supply. the range of v dd is 4.75 v to 5.25v. bypass v dd to gnd with a 10 f ceramic capacitor. gnd (pins 3, 6 and 16): ground. in + , in C (pins 4, 5): positive and negative differential analog inputs. typical input range 10.24v. refbuf (pin 7): reference buffer output. an onboard buffer nominally outputs 4.096 v to this pin. this pin is referred to gnd and should be decoupled closely to the pin with a 47 f ceramic capacitor. the internal buffer driving this pin may be disabled by grounding its input at refin. once the buffer is disabled, an external refer - ence may overdrive this pin in the range of 2.5 v to 5 v. a resistive load greater than 500 k can be placed on the reference buffer output. refin (pin 8): reference output/reference buffer input. an onboard bandgap reference nominally outputs 2.048v at this pin. bypass this pin with a 100 nf ceramic capacitor to gnd to limit the reference output noise. if more accu - racy is desired , this pin may be overdriven by an external reference in the range of 1.25v to 2.4v. cnv ( pin 9): convert input. a rising edge on this input powers up the part and initiates a new conversion. logic levels are determined by ov dd . chain (pin 10): chain mode selector pin. when low, the LTC2337-18 operates in normal mode and the rdl/sdi input pin functions to enable or disable sdo. when high, the LTC2337-18 operates in chain mode and the rdl/sdi pin functions as sdi, the daisy-chain serial data input. logic levels are determined by ov dd . busy (pin 11): busy indicator. goes high at the start of a new conversion and returns low when the conversion has finished. logic levels are determined by ov dd . rdl/sdi (pin 12): when chain is low, the part is in nor- mal mode and the pin is treated as a bus enabling input. when chain is high, the part is in chain mode and the pin is treated as a serial data input pin where data from another adc in the daisy chain is input. logic levels are determined by ov dd . sck ( pin 13): serial data clock input. when sdo is enabled , the conversion result or daisy-chain data from another adc is shifted out on the rising edges of this clock msb first. logic levels are determined by ov dd . sdo (pin 14): serial data output. the conversion result or daisy-chain data is output on this pin on each rising edge of sck msb first. the output data is in 2 s complement format. logic levels are determined by ov dd . ov dd (pin 15): i/o interface digital power. the range of ov dd is 1.71 v to 5.25 v. this supply is nominally set to the same supply as the host interface (1.8v, 2.5v, 3.3v, or 5v). bypass ov dd to gnd with a 0.1f capacitor. ltc 2337-18 233718f
9 for more information www.linear.com/LTC2337-18 func t ional b lock diagra m ti m ing diagra m refbuf = 2.5v to 5v refin = 1.25v to 2.4v in + v dd = 5v ov dd = 1.8v to 5v in ? v ddlbyp = 2.5v chain 0.63 buffer 2 reference buffer r 4r cnv gnd busy sdo sck rdl/sdi control logic ldo 2.048v reference 18-bit sampling adc spi port + ? 233718 bd01 15k 4r r nap convert acquire hold d15 d17 d16 d2 d1 d0 sdo sck cnv chain, rdl/sdi = 0 busy 233718 td01 conversion timing using the serial interface ltc 2337-18 233718f
10 for more information www.linear.com/LTC2337-18 a pplica t ions i n f or m a t ion o vervie w the LTC2337-18 is a low noise, high speed 18- bit succes- sive approximation register ( sar) adc with fully differential inputs. operating from a single 5 v supply, the LTC2337-18 has a 10.24 v true bipolar input range, making it ideal for high voltage applications which require a wide dynamic range. the LTC2337-18 achieves 4 lsb inl maximum, no missing codes at 18-bits and 100db snr. the LTC2337-18 has an onboard single- shot capable reference buffer and low drift (20ppm/ c max) 2.048 v temperature- compensated reference. the LTC2337-18 also has a high speed spi- compatible serial interface that supports 1.8 v, 2.5v , 3.3 v and 5 v logic while also featuring a daisy- chain mode. the fast 500ksps throughput with no cycle latency makes the LTC2337-18 ideally suited for a wide variety of high speed applications. an internal oscillator sets the conversion time, easing external timing considerations. the LTC2337-18 dissipates only 35mw and automatically naps between conversions, leading to reduced power dissipation that scales with the sampling rate. a sleep mode is also pro - vided to reduce the power consumption of the LTC2337-18 to 300 w for further power savings during inactive periods. c onver ter o pera tion the LTC2337-18 operates in two phases. during the acquisition phase, the charge redistribution capacitor d/a converter ( cdac) is connected to the outputs of the resistor divider networks that pins in + and in C drive to sample an attenuated and level-shifted version of the differential analog input voltage as shown in figure 3. a rising edge on the cnv pin initiates a conversion. dur- ing the conversion phase, the 18- bit cdac is sequenced through a successive approximation algorithm, effectively comparing the sampled input with binary-weighted frac- tions of the reference voltage ( e.g. v refbuf /2, v refbuf /4 v refbuf /262144) using the differential comparator. at the end of conversion, the cdac output approximates the sampled analog input. the adc control logic then prepares the 18-bit digital output code for serial transfer. t ransfer f unction the LTC2337-18 digitizes the full-scale voltage of 5 ? refbuf into 2 18 levels, resulting in an lsb size of 156 v figure 2. LTC2337-18 transfer function with refbuf = 4.096v . the ideal transfer function is shown in figure 2. the output data is in 2 s complement format. a nalog i nput the analog inputs of the LTC2337-18 are fully differential to maximize the signal swing that can be digitized. the analog inputs can be modeled by the equivalent circuit shown in figure 3. the back- to - back diodes at the inputs form clamps that provide esd protection. each input drives a resistor divider network that has a total imped - ance of 2k . the resistor divider network attenuates and level shifts the 2.5 ? refbuf true bipolar signal swing of each input to the 0-refbuf input signal swing of the adc core. in the acquisition phase, 45pf ( c in ) from the sam - pling cdac in series with approximately 50 (r on ) from the on- resistance of the sampling switch is connected to input voltage (v) 0v output code (two?s complement) ?1 lsb 233718 f02 011...111 011...110 000...001 000...000 100...000 100...001 111...110 1 lsb bipolar zero 111...111 fsr/2 ? 1lsb ?fsr/2 fsr = +fs ? ?fs 1lsb = fsr/262144 figure 3. the equivalent circuit for the differential analog input of the LTC2337-18 r on 50 400 c in 45pf r on 50 0.63 ? v refbuf c in 45pf in + in ? bias voltage 1.6k 1.6k 400 0.63 ? v refbuf 233718 f03 ltc 2337-18 233718f
11 for more information www.linear.com/LTC2337-18 a pplica t ions i n f or m a t ion figure 4. input signal chain the output of the resistor divider network. any unwanted signal that is common to both inputs will be reduced by the common mode rejection of the adc core and resistor divider network. the inputs of the adc core draw a current spike while charging the c in capacitors during acquisition. i nput d rive c ircuits a low impedance source can directly drive the high im- pedance inputs of the LTC2337-18 without gain error. a high impedance source should be buffered to minimize settling time during acquisition and to optimize the dis- tortion performance of the adc. minimizing settling time is important even for dc inputs, because the adc inputs draw a current spike when entering acquisition. for best performance, a buffer amplifier should be used to drive the analog inputs of the LTC2337-18. the amplifier provides low output impedance to minimize gain error and allows for fast settling of the analog signal during the acquisition phase. it also provides isolation between the signal source and the adc inputs which draw a small current spike during acquisition. input filtering the noise and distortion of the buffer amplifier and signal source must be considered since they add to the adc noise and distortion. noisy input signals should be filtered prior to the buffer amplifier input with a low bandwidth filter to minimize noise. the simple 1- pole rc lowpass filter shown in figure 4 is sufficient for many applications. the input resistor divider network, sampling switch on- resistance (r on ) and the sample capacitor (c in ) form a second lowpass filter that limits the input bandwidth to the adc core to 7 mhz. a buffer amplifier with a low noise density must be selected to minimize the degradation of the snr over this bandwidth. high quality capacitors and resistors should be used in the rc filters since these components can add distortion. npo and silver mica type dielectric capacitors have excellent linearity. carbon surface mount resistors can generate distortion from self heating and from damage that may occur during soldering. metal film surface mount resistors are much less susceptible to both problems. single-ended-to-differential conversion for single-ended input signals, a single-ended-to- differen - tial conversion cir cuit must be used to produce a differential signal at the inputs of the LTC2337-18. the lt1469 high speed dual operational amplifier is recommended for per- forming single- ended - to- differential conversions as shown in figure 5 a. in this case, the first amplifier is configured as a unity gain buffer and the single-ended input signal directly drives the high impedance input of this amplifier. figure 5 b shows the resulting fft when the lt1469 is used to drive the LTC2337-18 in this configuration. 6600pf 500 bw = 48khz single-ended- to-differential driver single-ended input signal LTC2337-18 in + in ? 233718 f04 lt1469 233718 f05a 10.24v 10.24v out1 out2 3 1 7 6 5 2 + ? 4.99k 4.99k 10.24v + ? figure 5a. lt1469 converting a 10.24v single-ended signal to a 20.48v differential input signal frequency (khz) ?180 amplitude (dbfs) ?60 ?40 ?20 ?80 ?100 ?120 ?140 ?160 0 233718 f05b snr = 100db thd = ?115db sinad = 99.9db sfdr = ?119db 0 50 100 150 250 200 figure 5b. 128k point fft plot with f in = 2khz for circuit shown in figure 5a ltc 2337-18 233718f
12 for more information www.linear.com/LTC2337-18 a pplica t ions i n f or m a t ion figure 7a.LTC2337-18 internal reference circuit fully differential inputs to achieve the full distortion performance of the ltc2337 - 18, a low distortion fully differential signal source driven through the lt1469 configured as two unity gain buffers as shown in figure 6 can be used to get the full data sheet thd specification of C115db. figure 6. lt1469 buffering a fully differential signal source lt1469 233718 f06 3 1 2 + ? 5 7 6 + ? 10.24v 10.24v 10.24v 10.24v internal reference with internal buffer the LTC2337-18 has an on-chip, low noise, low drift (20ppm/ c max), temperature compensated bandgap reference that is factory trimmed to 2.048 v. it is internally connected to a reference buffer as shown in figure 7 a and is available at refin (pin 8). refin should be bypassed to gnd with a 100nf ceramic capacitor to minimize noise. the reference buffer gains the refin voltage by 2 to 4.096 v at refbuf (pin 7). so the input range is 10.24 v, as shown in table 1. bypass refbuf to gnd with at least a 47f ceramic capacitor (x7r, 10v, 1210 size) to compensate the reference buffer and minimize noise. LTC2337-18 bandgap reference 233718 f07a 47f 100nf 6.5k refbuf refin 15k 6.5k reference buffer gnd external reference with internal buffer if more accuracy and/or lower drift is desired, refin can be easily overdriven by an external reference since a 15 k resistor is in series with the reference as shown in figure ?7 b. refin can be overdriven in the range from 1.25v to 2.4 v. the resulting voltage at refbuf will be 2??? refin. so the input range is 5 ? refin, as shown in table 2. linear technology offers a portfolio of high performance references designed to meet the needs of many applications. with its small size, low power, and high accuracy, the ltc6655-2.048 is well suited for use with the LTC2337-18 when overdriving the internal reference. the ltc6655-2.048 offers 0.025% ( max) initial accuracy and 2ppm/c ( max) temperature coefficient for high pre - cision applications . the ltc6655-2.048 is fully specified over the h-grade temperature range and complements the extended temperature range of the LTC2337-18 up to 125 c . bypassing the ltc6655-2.048 with a 2.7 f to 100 f ceramic capacitor close to the refin pin is recommended. adc r eference there are three ways of providing the adc reference. the first is to use both the internal reference and reference buffer. the second is to externally overdrive the internal reference and use the internal reference buffer. the third is to disable the internal reference buffer and overdrive the refbuf pin from an external source. the following tables give examples of these cases and the resulting bipolar input ranges. table 1. internal reference with internal buffer refin refbuf bipolar input range 2.048v 4.096v 10.24v table 2. external reference with internal buffer refin (overdrive) refbuf bipolar input range 1.25v (min) 2.5v 6.25v 2.048v 4.096v 10.24v 2.4v (max) 4.8v 12v table 3. external reference unbuffered refin refbuf (overdrive) bipolar input range 0v 2.5v (min) 6.25v 0v 5v (max) 12.5v ltc 2337-18 233718f
13 for more information www.linear.com/LTC2337-18 a pplica t ions i n f or m a t ion figure7b. using the ltc6655-2.048 as an external reference figure 7c. overdriving refbuf using the ltc6655-5 figure 8. cnv w aveform showing burst sampling LTC2337-18 bandgap reference ltc6655-2.048 233718 f07b 47f 2.7f 6.5k refbuf refin 15k 6.5k reference buffer gnd LTC2337-18 gnd bandgap reference ltc6655-5 233718 f07c 47f 6.5k refbuf refin 15k 6.5k reference buffer external reference unbuffered the internal reference buffer can also be overdriven from 2.5v to 5 v with an external reference at refbuf as shown in figure 7 c. so the input ranges are 6.25 v to 12.5v, respectively, as shown in table 3. to do so, refin must be grounded to disable the reference buffer. a 13 k resis - tor loads the refbuf pin when the reference buffer is disabled. to maximize the input signal swing and cor- responding snr , the ltc6655-5 is recommended when overdriving refbuf. the ltc6655-5 offers the same small size, accuracy, drift and extended temperature range as the ltc6655-2.048. by using a 5 v reference, an snr of 102db can be achieved. bypassing the ltc6655-5 with a 47 f ceramic capacitor (x5r, 0805 size) close to the refbuf pin is recommended. the refbuf pin of the LTC2337-18 draws a charge ( q conv ) from the external bypass capacitor during each conversion cycle. if the internal reference buffer is overdriven, the external reference must provide all of this charge with a dc current equivalent to i refbuf = q conv /t cyc . thus, the dc current draw of refbuf depends on the sampling rate and output code. in applications where a burst of samples is taken after idling for long periods, as shown in figure ?8, i refbuf quickly goes from approximately 390 a to a maxi - mum of 0.8 ma for refbuf = 5 v at 500 ksps. this step in dc current draw triggers a transient response in the external cnv idle period idle period 233718 f08 reference that must be considered since any deviation in the voltage at refbuf will affect the accuracy of the output code. if an external reference is used to overdrive refbuf, the fast settling ltc6655-5 reference is recommended. internal reference buffer transient response for optimum transient performance, the internal reference buffer should be used. the internal reference buffer uses a proprietary design that results in an output voltage change at refbuf of less than 1 lsb when responding to a sudden burst of conversions. this makes the internal reference buffer of the LTC2337-18 truly single- shot capable since the first sample taken after idling will yield the same result as a sample taken after the transient response of the internal reference buffer has settled. figure 9 shows the transient responses of the LTC2337-18 with the internal reference buffer and with the internal reference buffer overdriven by the ltc6655-5, both with a bypass capacitance of 47f. d ynamic p erformance fast fourier transform ( fft ) techniques are used to test the adc s frequency response, distortion and noise at the rated throughput. by applying a low distortion sine wave and analyzing the digital output using an fft algorithm, the adc s spectral content can be examined for frequencies outside the ltc 2337-18 233718f
14 for more information www.linear.com/LTC2337-18 time (s) deviation from final value (lsb) 2 0 ?2 ?4 233718 f09 ?8 ?6 0 900800700600500400300200100 1000 internal reference buffer external source on refbuf ?180 amplitude (dbfs) ?60 ?40 ?20 ?80 ?100 ?120 ?140 ?160 0 233718 f10 snr = 100.4db thd = ?116db sinad = 100.3db sfdr = ?118db frequency (khz) 0 50 100 150 250 200 a pplica t ions i n f or m a t ion fundamental. the LTC2337-18 provides guaranteed tested limits for both ac distortion and noise measurements. signal-to-noise and distortion ratio (sinad) the signal-to-noise and distortion ratio ( sinad) is the ratio between the rms amplitude of the fundamental input frequency and the rms amplitude of all other frequency components at the a/d output. the output is band limited to frequencies from above dc and below half the sampling frequency. figure 10 shows that the LTC2337-18 achieves a typical sinad of 100 db at a 500 khz sampling rate with a 2khz input. signal-to-noise ratio (snr) the signal-to-noise ratio ( snr) is the ratio between the rms amplitude of the fundamental input frequency and the rms amplitude of all other frequency components except the first five harmonics and dc. figure 10 shows that the LTC2337-18 achieves a typical snr of 100 db at a 500khz sampling rate with a 2khz input. total harmonic distortion (thd) total harmonic distortion ( thd) is the ratio of the rms sum of all harmonics of the input signal to the fundamental itself. the out-of-band harmonics alias into the frequency band between dc and half the sampling frequency (f smpl /2). thd is expressed as: thd = 20log v2 2 + v3 2 + v4 2 ++ v n 2 v1 where v 1 is the rms amplitude of the fundamental frequency and v2 through v n are the amplitudes of the second through nth harmonics. p o w er c onsidera tions the LTC2337-18 provides two power supply pins: the 5 v power supply ( v dd ), and the digital input/ output interface power supply ( ov dd ). the flexible ov dd supply allows the LTC2337-18 to communicate with any digital logic operat - ing between 1.8 v and 5 v , including 2.5 v and 3.3 v systems. power supply sequencing the LTC2337-18 does not have any specific power supply sequencing requirements. care should be taken to adhere to the maximum voltage relationships described in the absolute maximum ratings section. the ltc2337 - 18 has a power-on reset ( por) circuit that will reset the LTC2337-18 at initial power-up or whenever the power supply voltage drops below 2 v. once the supply voltage reenters the nominal supply voltage range, the por will re-initialize the adc. no conversions should be initiated until 200 s after a por event to ensure the re-initialization period has ended. any conversions initiated before this time will produce invalid results. t iming and c ontrol cnv t iming the LTC2337-18 conversion is controlled by cnv. a ris - ing edge on cnv will start a conversion and power up figure 9. transient response of the LTC2337-18 figure 10. 32k point fft of the LTC2337-18 ltc 2337-18 233718f
15 for more information www.linear.com/LTC2337-18 a pplica t ions i n f or m a t ion figure 11. power supply current of the LTC2337-18 versus sampling rate. the LTC2337-18. once a conversion has been initiated, it cannot be restarted until the conversion is complete. for optimum performance, cnv should be driven by a clean low jitter signal. converter status is indicated by the busy output which remains high while the conversion is in progress. to ensure that no errors occur in the digitized results, any additional transitions on cnv should occur within 40 ns from the start of the conversion or after the conversion has been completed. once the conversion has completed, the LTC2337-18 powers down. acquisition a proprietary sampling architecture allows the LTC2337-18 to begin acquiring the input signal for the next conver - sion 527 ns after the start of the current conversion. this extends the acquisition time to 1.460 s, easing settling requirements and allowing the use of extremely low power adc drivers. (refer to the timing diagram.) internal conversion clock the LTC2337-18 has an internal clock that is trimmed to achieve a maximum conversion time of 1.5s. auto nap mode the LTC2337-18 automatically enters nap mode after a conversion has been completed and completely powers up once a new conversion is initiated on the rising edge of cnv. during nap mode, only the adc core powers down and all other circuits remain active. during nap, data from the last conversion can be clocked out. the auto nap mode feature will reduce the power dissipation of the LTC2337-18 as the sampling frequency is reduced. since full power is consumed only during a conversion, the adc core of the LTC2337-18 remains powered down for a larger fraction of the conversion cycle (t cyc ) at lower sample rates, thereby reducing the average power dissipation which scales with the sampling rate as shown in figure 11. sleep mode the auto nap mode feature provides limited power savings since only the adc core powers down. to obtain greater power savings, the LTC2337-18 provides a sleep mode. during sleep mode, the entire part is powered down except for a small standby current resulting in a power dissipation of 300 w. to enter sleep mode, toggle cnv twice with no intervening rising edge on sck. the part will enter sleep mode on the falling edge of busy from the last conversion initiated. once in sleep mode, a rising edge on sck will wake the part up. upon emerging from sleep mode, wait t wake seconds before initiating a conversion to allow the reference and reference buffer to wake up and charge the bypass capacitors at refin and refbuf. (refer to the timing diagrams section for more detailed timing information about sleep mode.) d igit al i nterf ace the LTC2337-18 has a serial digital interface. the flexible ov dd supply allows the LTC2337-18 to communicate with any digital logic operating between 1.8 v and 5 v, including 2.5v and 3.3v systems. the serial output data is clocked out on the sdo pin when an external clock is applied to the sck pin if sdo is enabled. clocking out the data after the conversion will yield the best performance. with a shift clock frequency of at least 40mhz, a 500 ksps throughput is still achieved. the serial output data changes state on the rising edge of sck and can be captured on the falling edge or next rising edge of sck. d17 remains valid till the first rising edge of sck. the serial interface on the LTC2337-18 is simple and straightforward to use. the following sections describe the operation of the LTC2337-18. several modes are provided depending on whether a single or multiple adcs share the spi bus or are daisy-chained. sampling frequency (khz) 0 supply current (ma) 8 7 6 5 3 1 4 2 0 400 200 233718 g18 500 300 100 v dd ov dd ltc 2337-18 233718f
16 for more information www.linear.com/LTC2337-18 ti m ing diagra m s normal mode, single device when chain = 0, the LTC2337-18 operates in normal mode. in normal mode, rdl/sdi enables or disables the serial data output pin sdo. if rdl/sdi is high, sdo is in high impedance. if rdl/ sdi is low, sdo is driven. figure ?1 2 shows a single LTC2337-18 operated in normal mode with chain and rdl/sdi tied to ground. with rdl/sdi grounded, sdo is enabled and the msb(d17) of the new conversion data is available at the falling edge of busy. this is the simplest way to operate the LTC2337-18. figure 12. using a single LTC2337-18 in normal mode cnv LTC2337-18 busy convert irq data in digital host clk sdo sck 233718 f12a rdl/sdi chain 233718 f12 convert convert t acq t acq = t cyc ? t hold nap nap cnv chain = 0 busy sck sdo rdl/sdi = 0 t busylh t dsdobusyl t sck t hsdo t sckh t quiet t sckl t dsdo t conv t cnvh t hold acquire t cyc t cnvl d17 d16 d15 d1 d0 1 2 3 16 17 18 acquire ltc 2337-18 233718f
17 for more information www.linear.com/LTC2337-18 ti m ing diagra m s normal mode, multiple devices figure 13 shows multiple LTC2337-18 devices operating in normal mode (chain = 0) sharing cnv, sck and sdo. by sharing cnv, sck and sdo, the number of required signals to operate multiple adcs in parallel is reduced. since sdo is shared, the rdl/sdi input of each adc must be used to allow only one LTC2337-18 to drive sdo at a time in order to avoid bus conflicts. as shown in figure 13, the rdl/sdi inputs idle high and are individually brought low to read data out of each device between conversions. when rdl/sdi is brought low, the msb of the selected device is output onto sdo. figure 13. normal mode with multiple devices sharing cnv, sck, and sdo 233718 f13 d17 a sdo sck cnv busy chain = 0 rdl/sdi b rdl/sdi a d17 b d16 b d1 b d0 b d15 b d16 a d15 a d1 a d0 a hi-z hi-z hi-z t en t hsdo t dsdo t dis t sckl t sckh t cnvl 1 2 3 16 17 18 19 20 21 34 35 36 t sck convert convert t quiet t conv t hold t busylh nap acquire acquire nap 233718 f13a rdl b rdl a convert irq data in digital host clk cnv LTC2337-18 sdo a sck rdl/sdi cnv LTC2337-18 sdo b sck rdl/sdi chain busy chain ltc 2337-18 233718f
18 for more information www.linear.com/LTC2337-18 ti m ing diagra m s chain mode, multiple devices when chain = ov dd , the LTC2337-18 operates in chain mode. in chain mode, sdo is always enabled and rdl/sdi ser ves as the serial data input pin ( sdi) where daisy-chain data output from another adc can be input. this is useful for applications where hardware constraints may limit the number of lines needed to interface to a large number of converters. figure 14 shows an example with two daisy-chained devices. the msb of converter a will appear at sdo of converter b after 18 sck cycles. the msb of converter a is clocked in at the sdi/rdl pin of converter b on the rising edge of the first sck. figure 14. chain mode timing diagram ov dd 233718 f14a convert irq data in digital host clk cnv LTC2337-18 busy sdo b sck rdl/sdi cnv LTC2337-18 sdo a sck rdl/sdi chain ov dd chain 233718 f14 d0 a d1 a d16 a d17 a d15 b d16 b d17 b sdo b sdo a = rdl/sdi b rdl/sdi a = 0 d0 b d1 b d15 a d16 a d17 a d0 a d1 a 1 2 3 16 17 18 19 20 34 35 36 t dsdobusyl t ssdisck t hsdisck t busylh t conv t hold t hsdo t dsdo t sckl t sckh t sckch t cnvl t cyc convert convert sck cnv busy chain = ov dd t quiet nap nap acquire acquire ltc 2337-18 233718f
19 for more information www.linear.com/LTC2337-18 ti m ing diagra m s sleep mode to enter sleep mode, toggle cnv twice with no intervening rising edge on sck as shown in figure 15. the part will enter sleep mode on the falling edge of busy from the last conversion initiated. once in sleep mode, a rising edge on sck will wake the part up. upon emerging from sleep mode, wait t wake seconds before initiating a conversion to allow the reference and reference buffer to wake up and charge the bypass capacitors at refin and refbuf. figure 15. sleep mode timing diagram 233718 f15 convert convert sleep nap and acquire chain = don?t care rdl/sdi = don?t care chain = don?t care rdl/sdi = don?t care cnv busy sck t busylh t wake t conv t cnvh convert convert sleep nap and acquire nap cnv busy sck t busylh t wake t conv convert t conv t cnvh t hold acquire t acq ltc 2337-18 233718f
20 for more information www.linear.com/LTC2337-18 b oar d l ayou t to obtain the best performance from the LTC2337-18 a printed circuit board is recommended. layout for the printed circuit board ( pcb) should ensure the digital and analog signal lines are separated as much as possible. in particular, care should be taken not to run any digital clocks or signals alongside analog signals or underneath the adc. recommended layout the following is an example of a recommended pcb layout. a single solid ground plane is used. bypass capacitors to the supplies are placed as close as possible to the supply pins. low impedance common returns for these bypass capacitors are essential to the low noise operation of the adc. the analog input traces are screened by ground. for more details and information refer to dc1908, the evaluation kit for the LTC2337-18. partial top silkscreen partial layer 1 component side ltc 2337-18 233718f
21 for more information www.linear.com/LTC2337-18 b oar d l ayou t partial layer 2 ground plane partial layer 3 power plane partial layer 4 bottom layer ltc 2337-18 233718f
22 for more information www.linear.com/LTC2337-18 b oar d l ayou t partial schematic of demoboard 100mhz max clk in 3.3vpp ain+ ain- int ext ref vref wp prog dc590 eeprom sdo sck cnv rdl busy db17 db16 9v-10v (nc) bypass caps for u10 + / - 10.24v + / - 10.24v * vref +3.3v +8.6v +3.3v +3.3v +5v +3.3v +3.3v +3.3v +3.3v +3.3v +3.3v v+ v- v+ v- clk db0 db1 db15 db10 db11 db12 db13 db14 db5 db6 db7 db8 db9 db3 db4 db2 db17 db16 clkout dc590_detect cnvst_33 cnv sck sdo busy rdl sck cnv sdo c48 10uf 6.3v c48 10uf 6.3v c15 0.1uf c15 0.1uf r8 33 ohm r8 33 ohm r32 0 ohm r32 0 ohm c14 0.1uf c14 0.1uf c4 0.1uf c4 0.1uf jp1 jp1 1 2 3 u3 nl17sz74 u3 nl17sz74 cp 1 d 2 q 3 gnd 4 q 5 clr 6 pr 7 vcc 8 r2 1k r2 1k c39 opt 1206 c39 opt 1206 r4 33 ohm r4 33 ohm tp4 tp4 c20 47uf 1210 10v c20 47uf 1210 10v c3 0.1uf c3 0.1uf j3 j3 1 3 2 4 5 6 7 8 9 10 11 13 12 14 c42 opt 0603 c42 opt 0603 r12 4.99k r12 4.99k r6 1k r6 1k c7 0.1uf c7 0.1uf c57 0.1uf 25v c57 0.1uf 25v r9 0 ohm r9 0 ohm c58 opt c58 opt c18 opt 0603 c18 opt 0603 c12 0.1uf c12 0.1uf c2 0.1uf c2 0.1uf r10 4.99k r10 4.99k + - u10b lt1469cs8 + - u10b lt1469cs8 5 6 7 c44 1.0uf 25v c44 1.0uf 25v c11 10uf c11 10uf u1 ltc233x- cms u1 ltc233x- cms 4 in+ 5 in- vdd 2 gnd 3 chain 10 gnd 6 refbuf 7 refin 8 cnv 9 vddlbyp 1 busy 11 rdl/sdi 12 sck 13 sdo 14 ovdd 15 gnd 16 c5 0.1uf c5 0.1uf r40 4.99k r40 4.99k r3 33 ohm r3 33 ohm tp3 tp3 r35 0 ohm r35 0 ohm u15 ltc6655bhms8-5 u15 ltc6655bhms8-5 vin 2 shdn 1 gnd 3 outf 7 gnd 8 gnd 4 outs 6 gnd 5 tp2 tp2 r36 0 ohm r36 0 ohm tp6 tp6 r11 4.99k r11 4.99k u4 nc7svu04p5x u4 nc7svu04p5x 4 5 3 2 r37 opt r37 opt r13 1k r13 1k jp2 jp2 1 2 3 c19 opt 0805 c19 opt 0805 c61 opt c61 opt r1 33 ohm r1 33 ohm r31 opt r31 opt c59 1.0uf 50v c59 1.0uf 50v c56 0.1uf c56 0.1uf tp7 tp7 - + u10a lt1469cs8 - + u10a lt1469cs8 1 2 3 8 4 r15 opt r15 opt c40 opt 1206 c40 opt 1206 tp1 tp1 j1 bnc j1 bnc r41 4.99k r41 4.99k c6 10uf 6.3v c6 10uf 6.3v e3 e3 r14 0 ohm r14 0 ohm c55 1.0uf 50v c55 1.0uf 50v tp5 tp5 c9 10uf 6.3v c9 10uf 6.3v p1 con-edge40-100 p1 con-edge40-100 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9 9 10 10 11 11 12 12 13 13 14 14 15 15 16 16 17 17 18 18 19 19 20 20 21 21 22 22 23 23 24 24 25 25 26 26 27 27 28 28 29 29 30 30 31 31 32 32 33 33 34 34 35 35 36 36 37 37 38 38 39 39 40 40 c46 2.2uf 10v c46 2.2uf 10v c49 100pf c49 100pf r7 1k r7 1k c60 0.1uf 25v c60 0.1uf 25v j6 bnc j6 bnc j4 bnc j4 bnc r5 49.9 1206 r5 49.9 1206 r16 opt r16 opt c43 0.1uf 25v c43 0.1uf 25v u2 nc7svu04p5x u2 nc7svu04p5x 4 5 3 2 r38 opt r38 opt c13 0.1uf c13 0.1uf u8 nc7sz04p5x u8 nc7sz04p5x 4 5 3 2 c10 0.1uf c10 0.1uf u7 24lc024-i /st u7 24lc024-i /st a0 1 a1 2 a2 3 vss 4 sda 5 scl 6 wp 7 vcc 8 u6 nc7sz66p5x u6 nc7sz66p5x 1 a 2 b gnd 3 4 oe vcc 5 u9 nc7sz04p5x u9 nc7sz04p5x 4 5 3 2 c17 0.1uf c17 0.1uf c16 0.1uf c16 0.1uf r39 0 ohm r39 0 ohm r34 opt r34 opt r17 2k r17 2k r33 0 ohm r33 0 ohm c47 opt 0603 c47 opt 0603 c1 0.1uf c1 0.1uf ltc 2337-18 233718f
23 for more information www.linear.com/LTC2337-18 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. p ackage descrip t ion please refer to http://www .linear.com/designtools/packaging/ for the most recent package drawings. msop (ms16) 0213 rev a 0.53 0.152 (.021 .006) seating plane 0.18 (.007) 1.10 (.043) max 0.17 ?0.27 (.007 ? .011) typ 0.86 (.034) ref 0.50 (.0197) bsc 16151413121110 1 2 3 4 5 6 7 8 9 note: 1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max 0.254 (.010) 0 ? 6 typ detail ?a? detail ?a? gauge plane 5.10 (.201) min 3.20 ? 3.45 (.126 ? .136) 0.889 0.127 (.035 .005) recommended solder pad layout 0.305 0.038 (.0120 .0015) typ 0.50 (.0197) bsc 4.039 0.102 (.159 .004) (note 3) 0.1016 0.0508 (.004 .002) 3.00 0.102 (.118 .004) (note 4) 0.280 0.076 (.011 .003) ref 4.90 0.152 (.193 .006) ms package 16-lead plastic msop (reference ltc dwg # 05-08-1669 rev a) ltc 2337-18 233718f
24 for more information www.linear.com/LTC2337-18 ? linear technology corporation 2013 lt 0913 ? printed in usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com/LTC2337-18 r ela t e d p ar t s typical a pplica t ion part number description comments adcs ltc2379-18/ltc2378-18/ ltc2377-18/ltc2376-18 18-bit, 1.6msps/1msps/500ksps/250ksps serial, low power adc 2.5v supply, differential input, 101.2db snr, 5v input range, dgc, pin-compatible family in msop-16 and 4mm 3mm dfn-16 packages ltc 2380-16/ltc2378-16/ ltc2377-16/ltc2376-16 16-bit, 2msps/1msps/500ksps/250ksps serial, low power adc 2.5v supply, differential input, 96.2db snr, 5v input range, dgc, pin-compatible family in msop-16 and 4mm 3mm dfn-16 packages ltc2369-18/ltc2368-18/ ltc2367-18/ltc2364-18 18-bit, 1.6msps/1msps/500ksps/250ksps serial, low power adc 2.5v supply, pseudo-differential unipolar input, 96.5db snr, 0v to 5v input range, pin-compatible family in msop-16 and 4mm 3mm dfn-16 packages ltc2370-16/ltc2368-16/ ltc2367-16/ltc2364-16 16-bit, 2msps/1msps/500ksps/250ksps serial, low power adc 2.5v supply, pseudo-differential unipolar input, 94db snr, 0v to 5v input range, pin-compatible family in msop-16 and 4mm 3mm dfn-16 packages ltc2389-18/ltc2389-16 18-bit/16-bit, 2.5msps parallel/serial adc 5v supply, pin-configurable input range, 99.8db/96db snr, parallel or serial i/o 7mm 7mm lqfp-48 and qfn-48 packages ltc1609 16-bit, 200ksps serial adc 10v, configurable unipolar/bipolar input, single 5v supply, ssop-28 and so-20 packages ltc1606/ltc1605 16-bit, 250ksps/100ksps parallel adcs 10v, 75mw/55mw 5v pin compatible adcs ltc1859/ltc1858/ ltc1857 16-/14-/12-bit, 8-channel 100ksps serial adcs 10v, softspan?, single-ended or differential inputs, single 5v supply, ssop-28 package dacs ltc 2756/ltc2757 18-bit, single serial/parallel i out softspan dac 1lsb inl/dnl, software-selectable ranges, ssop-28/7mm 7mm lqfp-48 package ltc2641 16-bit/14-bit/12-bit single serial v out dac 1lsb inl /dnl, msop-8 package, 0v to 5v output ltc2630 12-bit/10-bit/8-bit single v out dacs internal reference, 1lsb inl (12 bits), sc70 6-pin package references ltc6655 precision low drift low noise buffered reference 5v/2.5v/2.048v/1.2v, 2ppm/c, 0.25ppm peak-to-peak noise, msop-8 package ltc6652 precision low drift low noise buffered reference 5v/2.5v/2.048v/1.2v, 5ppm/c, 2.1ppm peak-to-peak noise, msop-8 package amplifiers lt1468/lt1469 single/dual 90mhz, 22v/s, 16-bit accurate op amp low input offset: 75v/125v lt1469 ?15v 233718 ta02 1 7 4 8 2 3 ? + ? + 4.99k LTC2337-18 in + v dd 5v in ? ?10.24v 10.24v 0v ?10.24v 10.24v 0v ?10.24v 10.24v 0v 15v 6 5 4.99k 47f refbuf 100nf refin lt1469 configured to convert a 10.24v single-ended signal to a 20.48v differential signal ltc 2337-18 233718f

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